As electronic industry evolves rapidly, multiple functions and high performance of electronic products are of interest. In order to meet packaging requirements of high integration and miniaturization, a single-layer circuit board that provides a plurality of active and passive components and interlayer connection has evolved to multi-layer boards, so as to expand the available circuit area on the circuit boards through interlayer connection under limited space.
Currently, in most semiconductor packages, semiconductor devices (e.g. semiconductor chips and chip-type passive components etc.) are disposed on the surface of the circuit board. The circuit board that is used as the carrier for semiconductor devices is usually a core layer that can be an insulating board or double-side copper foil substrate (insulating material with copper coil on both sides). The insulating board can be made of resin material, e.g. epoxy resin, polyimide, BT (Bismaleimide Trazine) resin, FR4 resin etc. Circuits are formed on the top and bottom sides of the core layer and plated through holes are formed therein, wherein the plated through holes can be used as electrical paths for electrically conducting circuits on the top and bottom surfaces of the core layer. Dielectric layers are further formed on the surfaces on both sides of the core layer and vias formed in the dielectric layers. Then, circuit patterning processes are performed, including photoresist layer exposure and development and circuit formation, to form build-up layers, the number of build-up layers depends on design requirements. Thereafter, a solder mask made of an insulating material is formed on the outermost layer of the build-up layers. Openings are formed in the solder mask to expose circuits on the outermost layer and used as electrically connecting pads. Electrically connecting elements such as bumps are then formed on the electrically connecting pads for connecting to external electronic devices.
As shown in FIG. 1, a cross-sectional schematic diagram depicts the structure of a circuit board used in traditional semiconductor packaging. The circuit board includes a core plate 10; circuit layers 11 and 11′ formed on the top and bottom surfaces of the core plate 10, respectively; build-up structures 13 and 13′ formed on the circuit layers 11 and 11′, respectively; solder masks 14 and 14′ formed on the surface of the build-up structures 13 and 13′. The solder masks 14 and 14′ are formed with openings 140 which expose a portion of the outer most layers of the build-up structures 13 and 13′ so as to be electrically connecting pads 131 and 131′.
When the above circuit board is applied in semiconductor packaging processes, the purposes of the top and bottom surfaces of the core plate 10 are different. The top surface of the core plate 10 is used for carrying and electrically connecting at least one semiconductor chip and passive component; while the bottom surface of the core plate 10 is implanted with a plurality of electrically connecting elements (e.g. solder balls). In addition, the circuit board is made up of different materials, i.e. the core plate 10, the build-up structures 13 and 13′ (formed from dielectric layer and metal circuits) and solder masks 14 and 14′. Since the Coefficient of Thermal Expansion (CTE) of the metal circuit layers and the dielectric layer and the solder masks are quite different, warpage is caused by temperature variation of a manufacturing process of the circuit board structure. Owing to temperature variation during manufacturing processes of the circuit board structure, for example, during baking, curing, thermal cycling processes, the circuit board structure has thermal stress that results in different amounts of deformation between the different layers. The circuit board may deform or even delaminated, or worse, cause semiconductor chip to be damaged due to the detrimental compression stress.
Along with the increase in the number of circuit layers and connecting element layout density, heat generated by highly integrated semiconductor chips in operation may significantly increase. Heat that is not efficiently dissipated may be adverse to the life of the semiconductor chips.
Thus, there is a need for a more robust circuit board structure that avoids warpage in large circuit boards due to thermal stress and increases heat dissipation efficiency for multi-layer circuit boards.